Regviz

Espressif Systems /ESP32-H2 /PCR /SYSCLK_CONF

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SYSCLK_CONF

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Espressif Systems/ESP32-H2/PCR/SYSCLK_CONF#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0LS_DIV_NUM0HS_DIV_NUM0SOC_CLK_SEL 0CLK_XTAL_FREQ

Description

SYSCLK configuration register

Fields

LS_DIV_NUM

clk_hproot is div1 of low-speed clock-source if clck-source is a low-speed clock-source such as XTAL/FOSC.
HS_DIV_NUM

clk_hproot is div3 of SPLL if the clock-source is high-speed clock SPLL.
SOC_CLK_SEL

This field is used to select clock source. 0: XTAL, 1: SPLL, 2: FOSC, 3: reserved.
CLK_XTAL_FREQ

This field indicates the frequency(MHz) of XTAL.

Links

()

Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data